This application relies for priority upon Korean Patent Application No. 2001-19304, filed on Apr. 11, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a method of forming a complementary metal oxide silicon (CMOS) type semiconductor device having dual gates.
A CMOS type semiconductor device is a device in which p-channel metal oxide semiconductor (PMOS) transistors along with n-channel metal oxide semiconductor (NMOS) transistors are formed to work cooperatively with each other. In the CMOS type semiconductor device, operation efficiency and speed are greatly improved as compared with a semiconductor device using only PMOS transistors and characteristic of bipolar transistors is presented. Accordingly, CMOS devices are commonly used in high performance semiconductor devices. In recent years, as the elements incorporated into devices are integrated to a high degree and minimized to increase the voltage characteristic and speed thereof, a dual gate type CMOS semiconductor device in which p-type and n-type impurities are implanted in polysilicon gates of corresponding impurity type transistor regions has been proposed and widely used. The dual gate type CMOS semiconductor device has the advantages of reinforcing the function of surface layer portions of channels and enabling symmetrical low voltage operation.
However, in the CMOS type semiconductor device having polysilicon gates, a thin depletion layer is formed between the polysilicon gates and a gate insulation layer since the operation voltage applied to the gates is contrary to the impurity type of the polycrystalline silicon gates. Particularly, as thickness of the gate insulation layer is decreased, a depletion of the polysilicon gate is intensified.
In the MOS transistors of the CMOS type semiconductor device, it is required that the gate insulation layer be formed to be relatively thin, for example, about 10 xc3x85, according to the conditions. Accordingly, the depletion of the polysilicon gate becomes more of an issue. For example, when boron ions escape from a polysilicon layer forming the gate, a boron concentration in the polysilicon layer adjacent to the gate insulating layer is reduced to raise a poly-gate depletion effect (PDE). Supposing that the PDE occurs and thereby the polysilicon gate forms an electric insulation layer of 3 xc3x85 at a lower end thereof, the gate insulation layer comes to be formed several ten percent as thick as the required thickness.
Specifically, when the gates of the PMOS transistors among the CMOS transistors are formed during the fabrication of the high performance dual poly-gate type CMOS semiconductor device, boron is usually used as a dopant implanted in the polysilicon gate layer. However, a problem that the boron is diffused and escaped into the channels through the thin gate insulating layer as well as that it is insufficiently implanted or activated may occur. That is, if the boron ions are discharged from the polysilicon gate layer during the impurity implantation, the boron concentration in the polysilicon gate layer adjacent to the gate insulating layer is reduced and thereby the PDE is more intensified.
To prevent the PDE, there has been proposed a method of using a metal gate instead of the polysilicon gate. When the metal gate instead of the polysilicon gate is used as a gate electrode, the PDE does not occur. Also, the resistance of gate lines can be reduced, thereby reducing the signal distortion due to the resistance-capacitor (RC) delay.
However, in this case, since the threshold voltage of the single metal gate can be increased and the metal elements can be diffused through the gate insulation layer, the reliability of the gate insulation layer is deteriorated. Thus, in the semiconductor device in which the threshold voltage should be reduced for purposes of low power consumption and high speed operation, using the metal gate may introduce drawbacks.
The threshold voltage problem usually occurs since the same type of metal is used as the gate metal in both the PMOS and NMOS transistor regions of the CMOS type semiconductor device. For example, when the metal of one kind having a fermi level between energy levels of conduction and valence bands of the semiconductor layer is used as a gate metal, the threshold voltage is increased about 0.5V compared with the dual poly-gate even though the metal has the same impurity and concentration as that of a doped channel layer.
To reduce the threshold voltage when using the metal of one kind as a gate metal, a method of doping an impurity of a type different than that of a channel dopant additionally in the doped channel layer can be considered. In the method, the threshold voltage is decreased, but the channels are formed in a body as well as a surface, thereby deteriorating the characteristics of the device.
Accordingly, a method of using metals of two kinds having different fermi levels or work functions instead of a single metal as gate electrodes in the PMOS and NMOS transistor regions has been proposed. In the method, a metal having a fermi level similar to the energy level of the conduction band of the silicon layer doped by an n+-type impurity is used as gate electrodes in the NMOS transistor region, and a metal having a fermi level similar to the energy level of the valence band of the silicon layer doped by a p+-type impurity is used as gate electrodes in the PMOS transistor region.
FIG. 1 to FIG. 4 are cross-sectional views illustrating a conventional method of forming gate electrodes of different metals in first and second impurity type transistor regions. Referring to FIG. 1, first and second transistor regions 14, 12 and an isolation layer 16 are formed to define element regions in a surface of a substrate 10. A gate insulation layer 18 and a gate layer 20 are then formed on the surface of the substrate 10. And then, the first gate layer 20 is removed from the surface of the substrate 10 in the second impurity transistor region 12. A portion 21 of the first gate layer 20 on the surface of the substrate 10 in the first impurity transistor region 14 remains, as shown in FIG. 2. Thereafter, as shown in FIG. 3, a second gate layer 30 is formed over the surface of the substrate 10 in the second impurity type transistor region 12. To form gate electrodes 23, 33, the remaining portion 21 of the first gate layer 20 and the second gate layer 30 over the surface of the substrate 10 in the first and second impurity type transistor regions 14, 12 are patterned. However, in the process described above, when the first gate layer 20 is partially removed, the gate insulation layer 18 to be positioned below the second gate layer is apt to be damaged. As a result, the characteristics of the second impurity type transistors may deteriorate.
Therefore, it is an object of the present invention to provide an improved method of forming a CMOS type semiconductor device which can prevent a poly-gate depletion effect (PDE).
It is another object of the present invention to provide an improved method of forming a CMOS type semiconductor device which can prevent the PDE and at the same time, decrease a threshold voltage of transistors to drive them in a high speed and a low power consumption.
It is other object of the present invention to provide an improved method of forming a CMOS type semiconductor device which can enhance the reliability of a gate insulation layer.
The present invention is directed to a method of forming a CMOS type semiconductor device. In accordance with the method, a first gate insulation layer and a first metal-containing layer are formed sequentially on a surface of a substrate in first and second impurity type transistor regions on which an isolation layer is formed. The first gate insulation layer on the surface of the substrate in the second impurity type transistor region is exposed by selectively etching the first metal-containing layer anisotropically. The first gate insulation layer on the surface of the substrate is removed in the second impurity type transistor region. A second gate insulation layer is formed on the surface of the substrate in the second impurity type transistor region. A second metal-containing layer is formed over the surface of the substrate on which the second gate insulation layer is formed. A first gate electrode is formed on the surface of the substrate in the first impurity type transistor region by patterning the first metal-containing layer. A second gate electrode is formed on the surface of the substrate in the second impurity type transistor region by patterning the second metal-containing layer.
In one embodiment, the first and second metal-containing layers can include a conductive nitride or oxide layer as well as a pure metal layer. Also, the first and second gate insulation layers can be formed by oxidizing the substrate thermally. Alternatively, the gate insulation layers can be formed of silicon nitrides or insulation metal oxides having a high dielectric constant with the relative dielectric constant in the range of more than 10, by a method such as a chemical vapor deposition (CVD), a sputtering, an atomic layer deposition (ALD) or the like. Accordingly, when the second gate insulation layer is formed through the thermal oxidation and the insulation oxides are not formed on the first metal-containing layer, the first gate electrode comes to have a shape in which the second metal-containing layer is stacked on the first metal-containing layer. That is, when the first gate electrode is formed by patterning the first metal-containing layer, the first gate electrode can be formed through a patterning at a state which does not remove the second metal-containing layer on the first metal-containing layer.
The method of the invention further includes forming a layer of a metal such as a tungsten or aluminum to increase the conductivity of the gate electrodes after the step of forming a second metal-containing layer. Also, the steps of forming first and second gate electrodes can be concurrently carried out through the same patterning process.
In the embodiment, when first and second impurities in the first and second impurity type transistor regions are p-type and n-type impurities, respectively, the channel layers in the first and second impurity type transistor regions are respectively n-type and p-type impurities. In this case, preferably, a fermi level of the first metal-containing layer has an energy level, for example in the range of less than 0.2V, similar to the valence band of the silicon layer in the first impurity type transistor region doped by a p+-type impurity, and a fermi level of the second metal-contained layer has an energy level, for example in the range of less than 0.2V, similar to the conduction band of the silicon layer in the second impurity type transistor region doped by an n+-type impurity.
Also, the step of removing the first gate insulation layer can be carried out by a wet or dry etching process.